A PDP includes a plurality of parallel linear scanning electrodes for scanning and discharging for display, a plurality of parallel linear sustaining electrodes for discharging for display that are arranged between the scanning electrodes, and a plurality of parallel linear addressing electrodes crossing orthogonally the scanning and sustaining electrodes, for providing data to be displayed. Display cells are formed in areas where these electrodes cross each other. Each of these electrodes is covered with dielectric. Discharge at each cell is controlled in accordance with the amount of the wall charge formed on the dielectric. In the interlaced scanning scheme, one frame, which corresponds to an interval for displaying one picture, consists of two fields of an even-numbered field and an odd-numbered field, and one field consists of about eight to fifteen subfields. In the progressive scanning scheme, one frame consists of one field, and a subfield may be referred to also as “sub-frame”. Each subfield contains a reset period of time, an address period of time, and a sustain period of time which has a variable length. The reset period is a period of time for resetting the state of wall charges of cells varied in the previous subfield. During the address period, a voltage is selectively applied to the addressing electrodes in accordance with the subfield data while scanning pulses are applied sequentially to the respective scanning electrodes, to thereby vary the state of the wall charges of the cells, so that the cells are selectively activated. During the sustain period, the cells selected and activated during the address period are discharged for display.
Setoguchi et al., in Japanese Unexamined Patent Publication JP 2002-116730 (A) laid open on Apr. 19, 2002, disclose a method for driving a plasma display panel, in which, in each subfield of a field, the difference between an addressing voltage applied to first electrodes and an addressing voltage applied to second electrodes during an address period is controlled to be larger than the difference between a resetting voltage applied to the first electrodes and a resetting voltage applied to the second electrodes during a reset period.
In order to initialize or equalize voltages developed by the wall charges in the cells, typically, a larger resetting pulse voltage is applied between scanning electrodes and sustaining electrodes, or alternatively a larger ramping voltage is applied between them, and then a smaller ramping voltage is applied between them. The known Vt closed curve represents thresholds for discharging in cells of a PDP in association with the relationship among the cell voltage VcXY representative of the sum of the voltage difference applied between the sustaining electrodes X's and the scanning electrodes Y's, and the wall voltage developed between the electrodes X's and Y's, and the cell voltage VcAY representative of the sum of the voltage difference applied between the addressing electrodes A's and the scanning electrodes Y's, and the wall voltage developed between the electrodes A's and Y's. The Vt closed curve is described in detail in Japanese Unexamined Patent Publication JP 2003-248455 (A), which is incorporated by reference herein in its entirety.